1. Field of the Invention
This invention relates generally to capacitive elements for circuit boards having improved decoupling capacitance reliability, and more particularly to a circuit board or chip carrier or the like and method of manufacturing the same wherein the board or chip carrier uses multiple layers of dielectric material yet achieves high capacitance.
2. Background Art
In the manufacture of circuit boards or chip carriers or the like it is desirable to create as high a capacitance as possible between various ground, voltage and signal planes to thereby minimize the amount of discrete decoupling capacitors required on the board surface. The equation for determining capacitance is C=eA/t where C is the capacitance, e is the dielectric constant or relative permittivity of the dielectric material, A is the available area, and t is the thickness of the dielectric material or the spacing between the plates of the capacitor. Thus to increase the capacitance of a capacitor of a given area one can select a material having an increased dielectric constant and/or decrease the thickness of the dielectric material. However, the selection of the dielectric material is often limited by many production and configuration limitations which leaves principal means of increasing the capacitance to a reduction in thickness of the dielectric material. However, a problem encountered with certain types of dielectric material especially epoxy impregnated glass cloth, but other materials as well, at thinner gauges is that any defects in the material in the form of pin holes or voids tend to extend from one surface to the other thus resulting in failure of the structure either under test conditions, or even worse they may pass testing but fail under field use conditions. Therefore it is desirable to form a circuit board or chip carrier having reduced thickness of the dielectric material for improved capacitance but with improved reliability.